咨询电话0551-6530 6032
产品详情
| Technology family | LVC |
| Supply voltage (min) (V) | 1.65 |
| Supply voltage (max) (V) | 5.5 |
| Number of channels | 4 |
| Inputs per channel | 2 |
| IOL (max) (mA) | 32 |
| IOH (max) (mA) | -32 |
| Input type | Schmitt-Trigger |
| Output type | Push-Pull |
| Features | Over-voltage tolerant inputs, CMOS low power dissipation , Partial power down (Ioff) |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 125 |
| EM74LVC132AD | SOP-14L | plastic small outline package; 14 leads; body width 3.9 mm |
| EM74LVC132APW | TSSOP-14L | plastic thin shrink small outline package; 14 leads; body width 4.4 mm |
- Wide supply voltage range from 1.2 V to 5.5 V
- Overvoltage tolerant inputs to 5.5 V
- CMOS low power dissipation
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 250 mA
- Direct interface with TTL levels
- Complies with JEDEC standard:
- • JESD8-7A (1.65 V to 1.95 V)
- • JESD8-5A (2.3 V to 2.7 V)
- • JESD8-C (2.7 V to 3.6 V)
- • JESD36 (4.5 V to 5.5 V)
- ESD protection:
- • HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000 V
- • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
- Multiple package options
The EM74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
